In the field of semiconductor integrated circuit design, it is important that a layout of an integrated circuit be thoroughly checked before committing to the fabrication of the integrated circuit. Design errors that escape early detection result in significant problems for manufacturers of integrated circuits, including loss in time to market and costly retooling. Errors may be produced during the design stage, document editing stage, or substrate fabrication stage. Because the stages of producing an integrated circuit device involve many distinct groups responsible for generating different data necessary to produce the integrated circuit, verifying the data generated by the various groups is a tedious and time consuming task. More importantly, efforts using conventional methods to verify a design may not result in the identification of all of the errors.
In producing an integrated circuit, various implant layers are created in a substrate to form elements of the devices implementing a circuit. Mask layers are required to form the various implant layers as well as metal layers necessary to form the integrated circuit device. Similarly, tagging layers are used to track blocks, often called intellectual property (IP) blocks, within a design. In a programmable logic device, for example, circuit elements formed in a substrate may be connected by a plurality of metal layers and vias. The various layers may be formed by a different group of engineers using different tools and having different requirements and criteria for creating the data related to their layers or processes. Accordingly, verifying the layout of an integrated circuit is a difficult task.
One area requiring verification in the production of an integrated circuit is the verification of layout-versus-schematic (LVS). After a schematic is generated for a given circuit, a layout of the various layers of an integrated circuit is created. The layout-versus-schematic verification process confirms that the physical layout of the integrated circuit implements the circuit design of the schematic. Conventional processes for providing LVS verification generate a layout file by extraction, and compare the extracted file for the layout to the schematic. For example, an extraction tool may create a netlist based upon the layout, and compare the created netlist to a netlist for the schematic.
However, for each generation of a product, a new LVS physical verification file needs to be defined for the particular process node. In the new process node, additional elements are defined, layer generation algorithms change, and processing steps change. Because of the changes involved with each new technology node, additions, modifications, and deletions must be made to the LVS flow manually by the integrated circuit computer aided design (IC CAD) engineers responsible for the physical flow. This manual process may be time consuming because of the time required to coordinate between the technology development (TD) team, the IC CAD team, and the IC design (ICDES) team. Furthermore, the process is error-prone because conventional LVS rule files use implant layers only to identify particular devices, but do not exclude unwanted implant layers.
Currently, the LVS modification flow involves an IC CAD engineer performing the manual modification necessary to support the new process node. However, a successful modification process is highly dependent on the skill and experience of the IC CAD engineer and the engineer's understanding of the process technology. It is then followed by a peer LVS review within the IC CAD team for locating potential pitfalls visually. Finally, a LVS review is performed again with the ICDES team and the TD group for final approval. However, this process presents a lot of challenges since many TD engineers and ICDES engineers may not understand the underlaying LVS syntax and software engine. The verification process is further complicated by the need for multiple LVS rules files to be written for multiple tools and multiple foundries.
Accordingly, there is a need for an improved method of circuit for verifying a layout of an integrated circuit.